Advanced circuit design techniques have resulted in increasingly complex circuits, both at the integrated circuit and printed circuit board level of electronic design. Diminished physical access is unfortunate consequence of denser designs and shrinking interconnect pitch. Testability is needed so that the finished product is both controllable and observable during test and debug. Any manufacturing defect is preferably detectable during final test before product is shipped. This basic necessity is difficult to achieve for complex designs without taking testability into account and the logic design phase so that automatic test equipment can test the product. A popular test architecture is the scan path architecture disclosed in U.S. patent application Ser. Nos. 07/391,751 (Attorney Docket No. TI-14158) and 07/391,801 (Attorney Docket No. TI-14421), to Whetsel, both filed Aug. 9, 1989, and the entire issue of the Texas Instruments Technical Journal, Vol. 5, No. 4, all of which are incorporated by reference herein.
However, if the original design for the circuit for which testing is desired has more than one clock, then the testing procedure is much more complex. The clocks will either be asynchronous or synchronous with different frequencies. In such cases, a single "run" cycle (or "test execute" cycle) needs to be correctly synchronized between portions of the logic controlled by different clock frequencies.
One solution would be to partition circuit modules controlled by different clock frequencies and treat each module as an independent design. The scan paths would be implemented in each module separately with independent scan paths. Using this method, only one module could be tested at a time and the test time would be dominated by the modules clocked by the slowest clock or with the longest scan path. Thus, this method entails more test logic and more test time.
Therefore, a need has arisen for a scan path test architecture which allows efficient testing of circuits using multiple clock frequencies.